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cm - a510 com reference guide
introduction revised november 2010 cm - a510 reference guide 2 ? 2010 compulab ltd. all rights reserved. no part of this document may be photocopied, reproduced, stored in a retrieva l system, or transmitted, in any form or by any means whether, electronic, mechanical, or otherwise without the prior written permission of compulab ltd. . no warranty of accuracy is given concerning the contents of the information contained in this publication. to the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by compulab ltd. , its subsidiaries or employees for any direct or indirect los s or damage caused by omissions from or inaccuracies in this document. compulab ltd. reserves the right to change details in this publication without notice. product and company names herein may be the trademarks of their respectiv e owners. compulab ltd. malat bldg., technion, haifa 32000, israel tel: +972 (4) 8290100 http://www.compulab.co.il fax: +972 (4) 8325251
table of contents revised november 2010 cm - a510 reference guide 3 table of contents 1 introduction ................................ ................................ ................................ .............. 6 1.1 about this document ................................ ................................ ................................ ...... 6 1.2 cm - a510 part number legend ................................ ................................ ....................... 6 1.3 re lated documents ................................ ................................ ................................ .......... 6 2 overview ................................ ................................ ................................ ........................ 7 2.1 highlights ................................ ................................ ................................ ......................... 7 2.2 block diagra m ................................ ................................ ................................ ................. 8 2.3 cm - a510 features ................................ ................................ ................................ ........... 9 3 core system componen ts ................................ ................................ .................. 11 3.1 armad a 510 soc ................................ ................................ ................................ ............ 11 3.2 multimedia system ................................ ................................ ................................ ........ 12 3.2.1 video decode unit (vmeta) ................................ ................................ ................. 12 3.2.2 graphics processing unit ................................ ................................ ...................... 12 3.3 memory ................................ ................................ ................................ .......................... 13 3.3.1 dram ................................ ................................ ................................ ................... 13 3.3.2 spi flash ................................ ................................ ................................ ............... 13 3.3.3 nand flash ................................ ................................ ................................ ......... 13 4 peripheral interface s ................................ ................................ ....................... 14 4.1 display interface ................................ ................................ ................................ ............ 15 4.2 gigabit ethernet ................................ ................................ ................................ ............. 16 4.2.1 primary gigabit ethernet ................................ ................................ ...................... 16 4.2.2 secondary gigabit ethernet ................................ ................................ .................. 17 4.3 pci express ................................ ................................ ................................ .................... 18 4.4 sata ................................ ................................ ................................ ............................. 18 4.5 usb 2.0 ................................ ................................ ................................ .......................... 19 4.6 wlan ................................ ................................ ................................ ............................ 20 4.7 audio ................................ ................................ ................................ .............................. 21 4.7.1 analog audio ................................ ................................ ................................ ........ 21 4.7.2 i2s ................................ ................................ ................................ ......................... 22 4.7.3 s/pdif ................................ ................................ ................................ ................... 23 4.8 ua rt?s ................................ ................................ ................................ .......................... 24 4.9 rs232 ................................ ................................ ................................ ............................. 24 4.10 mmc / sd / sdio ................................ ................................ ................................ ..... 25 4.11 touch - screen ................................ ................................ ................................ ............. 26 4.12 gpio ................................ ................................ ................................ .......................... 27 4.13 camera interface ................................ ................................ ................................ ....... 28 4.14 i 2 c ................................ ................................ ................................ .............................. 29 4.15 spi ................................ ................................ ................................ ............................. 30
table of contents revised november 2010 cm - a510 reference guide 4 4.16 ssp ................................ ................................ ................................ ............................ 30 4.17 jtag ................................ ................................ ................................ ......................... 31 5 system logic ................................ ................................ ................................ .............. 32 5.1 power management ................................ ................................ ................................ ........ 32 5.1.1 power rails ................................ ................................ ................................ ........... 32 5.1.2 low power mode ................................ ................................ ................................ .. 32 5.2 reset ................................ ................................ ................................ ............................... 32 5.3 boot options ................................ ................................ ................................ .................. 32 5.4 system and miscellaneous signals ................................ ................................ ................ 33 5.5 signal multiplexing characteristics ................................ ................................ ............... 33 5.6 rtc ................................ ................................ ................................ ................................ 34 5.7 led ................................ ................................ ................................ ................................ 34 6 baseboard interface ................................ ................................ ........................... 35 6.1 connector pin - out ................................ ................................ ................................ .......... 35 6.2 connector type ................................ ................................ ................................ .............. 38 6.3 mechanical drawings ................................ ................................ ................................ ..... 38 6.4 standoffs ................................ ................................ ................................ ........................ 40 7 operational characte ristics ................................ ................................ ....... 41 7.1 absolute maximum ratings ................................ ................................ .......................... 41 7.2 recommended o perating conditions ................................ ................................ ............ 41 7.3 dc electrical characteristics ................................ ................................ ......................... 41 7.4 power consumption ................................ ................................ ................................ ....... 41 7.5 esd performance ................................ ................................ ................................ ........... 41 7.6 thermal characteristics ................................ ................................ ................................ . 42 7.7 operating temperature ranges ................................ ................................ ...................... 42 8 application notes ................................ ................................ ................................ .. 43 8.1 baseboard design guidelines ................................ ................................ ........................ 43 8.2 baseboard troublesh ooting ................................ ................................ ........................... 43 8.3 ethernet magnetics? implementation ................................ ................................ ............. 44 8.3.1 magnetics? selection ................................ ................................ ............................. 44 8.3.2 magnetics? connection ................................ ................................ ......................... 44 8.4 heat - plate integration ................................ ................................ ................................ ..... 44
revision information revised november 2010 cm - a510 reference guide 5 table 1 revision notes date description november 2010 first release please check for a newer revision of this manual at compulab's web site ? http://www.compulab.co.il/ . compare the revision notes of the updated manual from the web site to those of the printe d or electronic version you have.
introduction revised november 2010 cm - a510 reference guide 6 1 introduction 1.1 about this document this document is part of a set of reference documents providing information necessary to operate and program compulab?s cm - a510 computer - on - module. 1.2 cm - a510 part number legend for cm - a510 p art number legend, please refer to the ?prices? section at compulab website: http://www.compulab.co.il/a510/html/a510 - cm - price.htm . 1.3 related documents for additional information, refer t o the documents listed in table 2 . table 2 related documents document location cm - a510 product developer resources http://www.compulab.co.il/ 88ap510 functional specifications 88ap510 hardware specifica tions
overview revised november 2010 cm - a510 reference guide 7 2 overview 2.1 highlights marvell? armada? 510 cpu, dual issue armv7, up to 1000 mhz up to 1024 mbyte ddr3 up to 512 mbyte flash disk, including file - system protection wlan / wifi 802.11b/g/n interface graphics controller supporting parallel rgb and vga interfaces with hd 1080p max imum resolution and dual - head operation h.264, mpeg - 4, mpeg - 2, vc - 1and additional video codecs implemented by the vmeta subsystem integrated gpu providing 2d / 3d graphics acceleration with opengl - es support sata - ii hard disk interface 2 x 1000 baset ether net ports 4 x high - speed usb ports pci express interface sdio / mmc interface camera interface port audio sub - system with speaker, microphone and s/pdif support touch - screen controller serial ports, i2c, gpio low standby and active power consumption small size: 75 x 65 x 8 mm the cm - a510 is a small computer - on - module board designed to serve as a building block in embedded applications. the cm - a510 has all the components required to run most up to date linux - based operating systems. ready - to - run packages ar e available from compulab. the small size and low power consumption of the cm - a510 allows its integration into portable and space - constrained designs, while its low price makes it an ideal selection for cost - sensitive applications. the cm - a510 delivers fa st processing and a rich multimedia user experience, in a low - power design that offers fast internet browsing, hd video playback, 3d graphics and high - speed connectivity. cm - a510 is based on a high - performance, low - power marvell? armada? 510 system - on - chip with an arm v6/v7 - compliant superscalar processor core, hardware graphics processing unit, video decoding acceleration hardware and a broad range of peripherals. for embedded applications, the cm - a510 provides a variety of display interfaces, pci express bus, two gigabit ethernet ports, high - speed usb ports, sata interface, serial ports, general - purpose i/o lines and many other essential functions. the user interface is supported by an enhanced graphics controller, usb interface for keyboard/mouse and aud io sub - system.
overview revised november 2010 cm - a510 reference guide 8 2.2 block diagram figure 1 cm - a510 block diagram n a n d c o n t r o l l e r s d r a m c o n t r o l l e r s h e e v a a r m v 7 d i s p l a y c o n t r o l l e r m m c / s d - 0 u s b 2 - 1 p o w e r m a n a g e m e n t c i r c u i t r y d d r 3 5 1 2 m b / 1 g b n a n d 1 2 8 m b / 5 1 2 m b g b e m a c a u d i o c o d e c w i f i b / g / n s d i o - 0 i 2 s a r m a d a 5 1 0 u s b 2 . 0 h u b 2 4 b i t p a r a l l e l r g b g b e - 0 m i c i n s t e r e o o u t 2 d / 3 d g r a p h i c s a c c e l e r a t o r g b e p h y v m e t a v i d e o d e c o d e r r t c s a t a 2 . 0 c o n t r o l l e r p c i e x p r e s s c o n t r o l l e r s a t a p c i e - 0 5 v d c u a r t - 0 a n a l o g v g a i 2 c - 0 i 2 c - 0 u s b 2 - 0 g b e - 1 g b e c o n t r o l l e r s / p d i f s / p d i f m m c / s d - 1 r s 2 3 2 x c v r c o m - a u a r t - 2 c a m e r a u a r t - 1 u s b 2 - 0 s p i - 0 s p i f l a s h ( b o o t a b l e ) 1 m b b t - 6 5 6 s p i - 1 g p i o t o u c h s c r e e n c o n t r o l l e r c o m - c c o m - b b a c k - u p p o w e r u s b 2 - 1 p c i e - 1
overview revised november 2010 cm - a510 reference guide 9 2.3 cm - a510 features the "option" column specifies the configuration code required to have the particular feature. "+" means that the feat ure is always available. table 3 cpu, memory and busses feature specifications option cpu marvell armada 510 cpu, 800 / 1000 mhz armv7 architecture, integrated fpu, wmmx2 l1 cache: 32 kb (i - cache), 32 kb (d - cache) l2 cache: 512 kb dma, interrupt controller, timers c ram 512 - 1024 mb, ddr3, 533 mhz, 32 - bit d nand flash disk 128 - 512 mbytes n boot flash 1 mb, bootable + pci express bus pci express base specification, revision 1.1. one or two lanes. note: second lane is shared wi th optional second ethernet controller + table 4 peripherals feature specifications option graphics controller 16/18/24 bit color, resolution up to 1920 x 1080, frame buffer in system ddr. display types support: tft (parallel rgb) , analog vga. dual - head support. + video acceleration vmeta video decode subsystem running at rate up to 500 mhz. supporting h.264, mpeg - 4, mpeg - 2 and vc - 1. part of armada 510 soc. + 2d / 3d graphics integrated gpu providing 2d / 3d graphics accelerati on with opengl - es support. part of armada 510 soc. + two host / slave usb2 high - speed port, 480 mbps u2 usb additional 2 x usb2 high - speed host ports, 480 mbps u4 armada 510 integrated mac + rtl8211d phy, 10/100/1000baset, activity led ?s e1 gigabit ethernet realtek rtl8111 controller, 10/100/1000baset, activity led?s e2 sata interface armada 510 integrated sata - ii controller + phy, 3gb/s speed + serial ports (uarts) 3 uart ports, 16550 compatible: com - a ? rs232 interface, partial modem controls, 250 kbps com - b ? 3.3v interface, rx / tx only, 900 kbps com - c ? 3.3v interface, partial modem controls, 900 kbps + camera interface direct camera sensor support, max resolution 1920 x 1080, pixel clock up to 50mhz. itu bt.656, digital rgb/ycbcr interface. + general purpose i/o up to 38 lines shared with other functions. can also be used as interrupt inputs. + keyboard & mouse usb or redirection from com port + mmc / sd mmc / sd / sdio support including sdhc up to 32gb + i2s compliant audio codec, stereo output, stereo line - in, differential mic input . a audio s/pdif output, consumer mode iec 60958 - 3 + touchscreen ctrl. tsc2046 touchscreen controller. supports 4 - wire resistive panels i rtc real time clock, powered by external lithium battery + wifi interface implements 802.11b/g/n wireless connectivity standard. broadcom 4319 802.11b/g/n chipset. on - board connector for external antenna. w table 5 electrical, mechanical and environmental specifications supply voltage single 5 v dc active power consumption 2 ? 5 w, depending on configuration and cpu speed standby/sleep consumption 50 - 200 mw, depending on configuration and mode dimensions 75 x 65 x 8 mm weight 31 gram mtbf > 100,000 hours
overview revised november 2010 cm - a510 reference guide 10 operation temperature (case) comm ercial: 0 o to 70 o c extended: - 20 o to 70 o c industrial: - 40 o to 85 o c storage temperature - 40 o to 85 o c relative humidity 10% to 90% (operation) 05% to 95% (storage) shock 50g / 20 ms vibration 20g / 0 - 600 hz connectors 2 x 140 pin, 0 .6 mm connector insertion / removal 50 cycles
core system components revised november 2010 cm - a510 reference guide 11 3 core system componen ts 3.1 armada 510 soc the marvell armada 510 is a high - performance, highly integrated, low - power soc with a high - end arm - compatible processor, a graphics processing unit, high definition vide o decoding acceleration hardware and a broad range of peripherals. the armada 510 integrates an armv6/v7 - compliant, high - speed, dual - issue sheeva cpu core with double precision integrated floating point unit (fpu) and wmmx2 coprocessor, 32 - kb l1 data cache , 32 - kb instruction cache and 512 - kb l2 cache. it also includes an advanced power management unit, an advanced 2d/3d graphics processing unit, display controllers and a high - definition video decoder. the armada 510 integrates the following hardware engines to enhance performance: high - definition video decoding unit (vmeta) 2d/3d graphics processing unit (gpu) power management unit supporting soc low power states, dynamic frequency scaling (dfs) and dynamic voltage scaling (dvs) two xor dma engines and 16 - ch annel peripheral dma controller figure 2 armada 510 block diagram
core syst em components revised november 2010 cm - a510 reference guide 12 3.2 multimedia system 3.2.1 video decode unit (vmeta) the video decode unit decodes the compressed video elementary stream to produce the reconstructed video frames for disp lay or further processing. vmeta supports the following video formats: h.264 mp/hp @l4.1 with arbitrary slice order vc1 ap @l3, mp @hl mpeg2 mp @hl divx hd compliant mpeg4 avs for additional details, please refer to section 9 of the ?88ap510 functional spe cifications?. 3.2.2 graphics processing unit the graphics processing unit (gpu) is a low - power, high - performance 2d/3d graphics core designed to support the opengl - es 2.0 graphics processing standards. the armada 510 gpu provides support for the following imagin g and video features: 3d features: opengl es 1.1/2.0 compliant 32 - bit floating point pipeline including shaders up to eight programmable elements per vertex unified vertex and pixel shaders dependent texture operation with high - performance alpha blend supp ort for eight simultaneous pixel textures and four simultaneous vertex textures point sampling, bi - linear sampling, tri - linear sampling, and cubic textures multi - sample anti - aliasing 2d features: bit, stretch, pattern blits and fast clear line drawing rect angle fill mono expansion for text rendering rop2, rop3, rop4 alpha blending 90 - /180 - /270 - degree rotation video data format conversion high - quality scaling for additional details, please refer to section 10 of ?88ap510 functional specifications?.
core system components revised november 2010 cm - a510 reference guide 13 3.3 memory 3.3.1 d ram the cm - a510 board is assembled with 512 or 1024 mbytes of ddr3. the dram interface is 32 - bits wide and runs with a 533 mhz clock. 3.3.2 spi flash the cm - a510 is assembled with 1 mbyte of spi nor flash. the spi nor flash is the primary non - volatile memory de vice of the cm - a510, used for the boot - loader and configuration blocks storage. 3.3.3 nand flash the cm - a510 is assembled with 128 or 512 mbytes of slc nand flash. the nand flash is the secondary non - volatile memory device of the cm - a510, used for os storage an d flash drive implementation.
peripheral interfaces revised november 2010 cm - a510 reference guide 14 4 peripheral interface s the cm - a510 implements a number of peripheral interfaces through the interface connectors (p1 and p2). the following notes apply to those interfaces: some interfaces/signals are available only with/withou t certain configuration options. each signal?s availability is noted in the ?signal description? table of each interface. certain interface pins can be configured as one of several signals. for pin multiplexing characteristics, please refer to chapter 5.5 . certain signals are available on more than one interface pin. only one interface pin can be used for each signal. all of the cm - a510 digital interfaces operate at 3.3v cmos voltage levels, unless otherwise not ed. certain software - configurable multi - purpose signals can only be configured on a group basis. only the entire group may be assigned with a specific function. signals within a group cannot be configured separately for different functions. signal configur ation grouping is noted in the ?signal description? table of each interface. the signals for each interface are described in the ?signal description? tables. the following notes summarize the column headers for these tables: ?signal name? ? the symbolic na me of each signal. ?pin#? ? the pin number on the interface connector. ?type? ? signal type. ?description? ? signal description. ?availability? ? certain signals are not available with/without certain configuration options. this column summarizes configura tion requirements for each signal. each interface signal can be one of the following types. signal type is noted in the ?signal description? tables for each signal ?o? ? digital output. ?i? ? digital input. ?io? ? digital input/output. ?ao? ? analog output . ?ai? ? analog input. ?od? ? open drain signal (not pulled up on the cm - a510 unless otherwise noted). ?ipu? ? open drain signal (pulled up on the cm - a510 unless otherwise noted).
peripheral interfaces revised november 2010 cm - a510 reference guide 15 4.1 display interface the cm - a510 display sub - system is based on the display con troller of the armada 510 soc. the display sub - system incorporates two independent display controllers supporting dual - head operation and features two separate display interfaces: 24 - bit parallel rgb analog vga. the display subsystem supports the following main features: display controller programmable pixel display modes (12, 16, 18 and 24 bits - per - pixel) programmable resolution of up to 1920 x 1080 overlay and image scaling for video and graphics hardware cursor rotation of 90 - , 180 - and 270 - degrees for a dditional details, please refer to section 11 of the ?88ap510 functional specifications?. table 6 display interface signals signal name pin # type description parallel rgb lcd_pclk p1 - 108 o pixel clock lcd_hsync p1 - 109 o hor izontal synchronization lcd_vsync p1 - 107 o vertical synchronization lcd_e p1 - 105 o pixel data enable rgb444 mode rgb565 mode rgb666 mode rgb888 mode lcd_d0 p1 - 75 o pixel data bit 0 red[4] red[3] red[2] red[0] lcd_d1 p1 - 76 o pixel data bit 1 red[5] re d[4] red[3] red[1] lcd_d2 p1 - 77 o pixel data bit 2 red[6] red[5] red[4] red[2] lcd_d3 p1 - 78 o pixel data bit 3 red[7] red[6] red[5] red[3] lcd_d4 p1 - 81 o pixel data bit 4 green[4] red[7] red[6] red[4] lcd_d5 p1 - 82 o pixel data bit 5 green[5] green[2] r ed[7] red[5] lcd_d6 p1 - 83 o pixel data bit 6 green[6] green[3] green[2] red[6] lcd_d7 p1 - 84 o pixel data bit 7 green[7] green[4] green[3] red[7] lcd_d8 p1 - 85 o pixel data bit 8 blue[4] green[5] green[4] green[0] lcd_d9 p1 - 87 o pixel data bit 9 blue[5] green[6] green[5] green[1] lcd_d10 p1 - 88 o pixel data bit 10 blue[6] green[7] green[6] green[2] lcd_d11 p1 - 89 o pixel data bit 11 blue[7] blue[3] green[7] green[3] lcd_d12 p1 - 90 o pixel data bit 12 - blue[4] blue[2] green[4] lcd_d13 p1 - 92 o pixel data bit 13 - blue[5] blue[3] green[5] lcd_d14 p1 - 93 o pixel data bit 14 - blue[6] blue[4] green[6] lcd_d15 p1 - 94 o pixel data bit 15 - blue[7] blue[5] green[7] lcd_d16 p1 - 95 o pixel data bit 16 - - blue[6] blue[0] lcd_d17 p1 - 96 o pixel data bit 17 - - blue [7] blue[1] lcd_d18 p1 - 97 o pixel data bit 18 - - - blue[2] lcd_d19 p1 - 99 o pixel data bit 19 - - - blue[3] lcd_d20 p1 - 100 o pixel data bit 20 - - - blue[4] lcd_d21 p1 - 101 o pixel data bit 21 - - - blue[5] lcd_d22 p1 - 102 o pixel data bit 22 - - - blue [6] lcd_d23 p1 - 104 o pixel data bit 23 - - - blue[7] vga vga_r p1 - 28 ao red video signal vga_g p1 - 30 ao green video signal vga_b p1 - 32 ao blue video signal vga_hsync p1 - 34 o horizontal synchronization vga_vsync p1 - 36 o vertical synchronization
peripheral interfaces revised november 2010 cm - a510 reference guide 16 4.2 giga bit ethernet the cm - a510 incorporates up to two full - featured gigabit ethernet interfaces. 4.2.1 primary gigabit ethernet the cm - a510 primary gigabit ethernet interface is implemented with the armada 510 gigabit ethernet controller and an on - board rtl8211d realt ek phy. the interface supports the following main features: fully compliant with ieee 802.3 standard 1000 mbps operation ? full duplex 10 / 100 mbps operation ? half and full duplex crossover detection and auto - correction auto - negotiation activity and spee d indicator led controls table 7 primary gigabit ethernet interface signals signal name pin # type description availability lan0_mdip0 p1 - 2 io lan0_mdin0 p1 - 4 io first pair in 1000base - t / transmit pair in 10base - t and 100base - t. lan0_mdip1 p1 - 1 io lan0_mdin1 p1 - 3 io second pair in 1000base - t / receive pair in 10base - t and 100base - t. lan0_mdip2 p1 - 10 io lan0_mdin2 p1 - 12 io third pair in 1000base - t. lan 0_mdip3 p1 - 9 io lan0_mdin3 p1 - 11 io forth pair in 1000base - t. lan0_led0 p1 - 6 o activity led output. active low. lan0_led1 p1 - 5 o 10 / 100 / 1000 led output. lan0_led2 p1 - 13 o 10 / 100 / 1000 + activity led output. only available with either ?e1? or ?e2? configuration options. note: the primary gigabit ether net interface is available only with either ?e1? or ?e2? configuration options. note: for magnetics? selection recommendations, please refer to section 8.3 of this document.
peripheral interfaces revised november 2010 cm - a510 reference guide 17 4.2.2 secondary gigabit ethernet the cm - a5 10 secondary gigabit ethernet interface is implemented with the rtl8111d realtek gigabit ethernet controller. the controller is connected to the pcie - 1 interface of the armada 510 soc. the interface supports the following main features: fully compliant wit h ieee 802.3 standard crossover detection and auto - correction auto - negotiation activity and speed indicator led controls table 8 secondary gigabit ethernet interface signals signal name pin # type description availability lan1 _mdip0 p2 - 2 io lan1_mdin0 p2 - 4 io first pair in 1000base - t / transmit pair in 10base - t and 100base - t lan1_mdip1 p2 - 1 io lan1_mdin1 p 2 - 3 io second pair in 1000base - t / receive pair in 10base - t and 100base - t lan1_mdip2 p2 - 10 io lan1_mdin2 p2 - 12 io third pair in 1000base - t lan1_mdip3 p2 - 9 io lan1_mdin3 p2 - 11 io forth pair in 1000base - t lan1_led0 p2 - 6 o link 10 + activity led output lan1_led1 p2 - 5 o link 100 + activity led output lan1_led 2 p2 - 13 o link 10 / 100 / 1000 + activity led output. only available with the ?e2? configuration option. note: the primary gigabit ethernet interface is available only with the ?e2? configuration option. note: for magnetics? selection recommendations, please refer to section 8.3 of this document.
peripheral interfaces revised november 2010 cm - a510 reference guide 18 4.3 pci express the cm - a510 features up to two pci express ports implemented with the armada 510 pci express controller. pcie - 0 port is always available. pcie - 1 port is multiplexed with the secondary gigabit ethernet inte rface. the pci express interface provides the following features: pci express base 1.1 compatible root complex port 2.5 ghz signaling for additional details, please refer to section 20 of ?88ap510 functional specifications?. table 9 pci express interface signals signal name pin # type description availability pcie - 0 interface pcie0_tx_p p2 - 114 o pcie0_tx_n p2 - 112 o pci express transmit data pair pcie0_rx_p p2 - 108 i pcie0_r x_n p2 - 106 i pci express receive data pair pcie0_clk_p p2 - 101 o pcie0_clk_n p2 - 99 o pci express reference clock pair pcie0_nclkreq p2 - 17 io pci express clock request input always available. pcie - 1 interface pcie1_tx_p p2 - 113 o pcie1_tx_n p2 - 111 o pci express transmit data pair pcie1_rx_p p2 - 107 i pcie1_rx_n p2 - 105 i pci express receive data pair pcie1_clk_p p2 - 83 o pcie1_clk_n p2 - 81 o pci express reference clock pair pcie1_nclkreq p2 - 15 io pci express clock request input only available without the ?e2? con figuration option. not e: pcie - 1 interface is available only without the ?e2? configuration option. 4.4 sata the cm - a510 incorporates a single sata - ii port implemented with the armada 510 sata - ii controller. the interface supports the following main features: fully compatible with t he sata - ii phase 1.0 specification sata - ii 3 gb/s data rate sata - ii power management compliant sata - ii device hot - swap compliant sata - ii native command queuing (ncq) for additional details, please refer to section 21 of the ?88ap510 functional specificatio ns?. table 10 sata - ii interface signals signal name pin # type description availability sata_tx+ p2 - 126 o sata_tx - p2 - 124 o sata - ii transmit data pair. sata_rx+ p2 - 120 i sata_ rx - p2 - 118 i sata - ii receive data pair. always available.
peripheral interfaces revised november 2010 cm - a510 reference guide 19 4.5 usb 2.0 the cm - a510 provides up to four usb 2.0 ports implemented with the armada 510 usb sub - system and an optional on - board usb 2.0 hub. the usb 2.0 interface provides the following features: complies with ehci (high - speed host controll er) complies with ohci (low - speed/full - speed host controller) complies with the usb 2.0 standard for high - speed (480m bit/s) functions table 11 usb 2.0 host interface signals signal name pin # type description availability usb 0 interface usb0_dp p2 - 132 aoi usb port 0 positive data usb0_dn p2 - 130 aoi usb port 0 negative data only available with either ?u2? or ?u4? configuration options. usb1 interface usb1_dp p2 - 138 aoi usb port 1 positive data usb1_dn p2 - 136 aoi usb port 1 negative data only available with either ?u 2? or ?u4? configuration options. usb1_cpen p1 - 128 o usb port 1 external 5v supply enable. active high. usb1_novc p2 - 140 ipu usb port 1 over current sense. only available with ?u4? configuration option. usb 2 interface usb2_dp p1 - 131 aoi usb port 2 positive data usb2_dn p1 - 129 aoi usb port 2 negative data usb2_cpen p1 - 126 o usb port 2 external 5v supply enable. active high. usb2_novc p2 - 138 ipu usb port 2 over current sense. only available with the ?u4? configuration option. usb3 interface usb3_dp p1 - 137 aoi usb port 3 positive data usb3_dn p1 - 135 aoi usb port 3 negative data usb3_cpen p1 - 133 o usb port 3 external 5v supply enable. active high. u sb3_novc p2 - 136 ipu usb port 3 over current sense. only available with the ?u4? configuration option. note: four usb ports are available only with the ?u4? configuration option.
peripheral interfaces revised november 2010 cm - a510 reference guide 20 4.6 wlan the cm - a510 incorporates full - featured 802.11 b/g/n capabilities, implemented with the usi wm - n - bm - 01 wlan controller modu le. the wm - n - bm - 01 is a complete ieee 802.11b/g/n solution based on the broadcom 4319 chipset. the cm - a510 wlan interface supports the following security features: wep (64 bit/128 bit) wpa tkip wpa2 the wm - n - bm - 01 is connected to the armada soc via the sd - 1 port. antenna connection the wm - n - bm - 01 requires a single 2.45ghz antenna. the antenna is connected via the onboard ufl high frequency connector j1. any type of 2.45ghz wlan antenna can be used. please refer to section 6.3 for connector location. table 12 j1 connector data manufacturer mfg. p/n mating connector hirose u.fl - r - mt(10) hirose u.fl - lp - 040 table 13 802.11b/g/n rf system specifications parame ter test condition typical value units frequency band 2.400 ? 2.497 ghz maximum receive level per < 8% - 10 dbm 1, 2, 5.5, 11 mbps 17 dbm 6, 9 mbps 15 dbm 11n (ht20) 14 dbm transmit power output 11n (ht40) 14 dbm @ 869mhz ~ 960mhz - 160 dbm/hz @ 1800mhz ~ 1990mhz - 160 dbm/hz wide - band noise @ 2110mhz ~ 2170mhz - 150 dbm/hz @ 1 mbps - 13 db @ 6 mbps - 30 db @ 11 mbps - 13 db @ 54 mbps - 30 db @ mcs7 - 30 db error vector magnitude @ mcs0 - 30 db 1 mbps, 8% per - 94 dbm 6 mbps, 10% per - 86 dbm 11 mbps, 8% per - 87 dbm 54 mbps, 10% per - 73 dbm 65 mbps, 10% per - 72 dbm receive sensitivity 135 mbps, 10% per - 68 dbm
peripheral interfaces revised november 2010 cm - a510 reference guide 21 4.7 audio 4.7.1 analog audio the cm - a510 analog audio subsystem is implemented with texas instruments tlv320aic23b audio codec. the an alog audio subsystem supports the following features: single ended stereo - line output single ended stereo - line input integrated electret - microphone biasing and buffering solution 8 - khz ? 96 - khz sampling - frequency support 100 - db snr multibit sigma - delta dac (a - weighted at 48 khz) 90 - db snr multibit sigma - delta adc (a - weighted at 48 khz) table 14 audio characteristics parameter test conditions min typ max unit headphone output 0 - db full - scale output voltage 1.0 vrms rload = 32 30 maximum output power, po rload = 16 40 signal - to - noise ratio, a - weighted (see note 2) 90 97 db pout = 10mw 0.1 % total harmonic distortion 1khz output pout = 20mw 1.0 % power supply rejection ratio 1 khz, 100 mvp - p 50 db prog rammable gain 1 khz output - 73 6 programmable - gain step size 1 mute attenuation 1 khz output 80 line input to adc input signal level (0 db) 1.0 vrms signal - to - noise ratio, a - weighted, 0 - db gain (see notes 1 and 2) fsample = 48 khz. 85 90 db dynamic range, a - weight ed, ?60 - db full - scale input (see note 2) 85 90 db total harmonic distortion, ?1 - db input, 0 - db gain - 80 db power supply rejection ratio 1 khz, 100 mvp - p 50 db adc channel separation 1 khz input tone 90 db programmable - gain step size monotonic 1.5 db mute attenuation 0db, 1 khz input tone 80 db 12 db input gain 10 20 input resistance 0 db input gain 30 35 k input capacitance 10 pf microphone input to adc input signal level (0 db) 1.0 vrms signal - to - noise ratio, a - weighted, 0 - db gain (see notes 1 and 2) 80 85 db dynamic range, a - weighted, ?60 - db full - scale input (see note 2) 80 85 db total harmonic distortion, ?1 - db input, 0 - db gain - 60 db power supply rejection ratio 1 khz, 100 mvp - p 50 db mute attenuation 0db, 1 khz input tone 60 80 db input resistance 8 14 k input capacitance 10 pf
peripheral interfaces revised november 2010 cm - a510 reference guide 22 microphone bias bias voltage 2.375 2.475 2.575 v bias - current source 3 ma for additional details, please refer to the tlv320aic23b datasheet, available from texas in struments. table 15 analog audio signals signal name pin # type description availability audio_out_r p2 - 139 ao right stereo mixer - channel amplified headphone output audio_out_ l p2 - 137 ao left stereo mixer - channel amplified headphone output audio_in_r p2 - 131 ai right stereo line input audio_in_l p2 - 133 ai left stereo line input mic_in p2 - 129 ai buffered amplifier input suitable for use with electret - microphone mic_bias p2 - 125 o microphone bias output, suitable for electret - microphone biasing, 2.475v nominal voltage. audio_gnd p2 - 123 p dedicated analog audio ground only available with the ?a? configuration option. note: the analog audio interface is available only with the ?a? configuration option. 4.7.2 i2s the cm - a510 i2 s interface is implemented with the armada 510 i2s controller. the interface supports the following main features: plain i2s, right - justified and left - justified formats an audio sample rate of 44.1/48/96 khz sample sizes of 16 - bit, 20 - bit, 24 - bit and 32 - bi t. for additional details, please refer to section 12 of ?88ap510 functional specifications?. table 16 i2s signals signal name pin # type description availability configuration? group i2s1_bclk p2 - 45 o bit clock i2s1_di p2 - 47 i receiver data in i2s1_do p2 - 49 o transmitter data out i2s1_lrclk p2 - 51 o left/right clock i2s1_mclk p2 - 53 o master clock always availabl e. digital audio note: i2s signals are multiplexed with signals used for other interfaces. for multiplexin g characteristics, please refer to section 5.5 of this document. note: i2s signals can only be configured on a group basis. only the entire group may be assigned with a specific function. individual i2s signals cannot be configured separately for different functions.
peripheral interfaces revised november 2010 cm - a510 reference guide 23 4.7.3 s/pdif the cm - a510 features an s/pdif interface implemented with the armada 510 s/pdif controller. the interface supports the following main features: compliant with the iec60958 - 1, iec60958 - 3 and i ec61937 specifications an audio sample rate of 44.1/48/96 khz sample sizes of 16 - bit, 20 - bit, 24 - bit and 32 - bit. for additional details, please refer to section 12 of the ?88ap510 functional specifications?. table 17 s/pdif sig nals signal name pin # type description availability s/pdif p2 - 41 o s/pdif transmitter data out always available. note: s/pdif signals are multiplexed with signals used for other interfaces. for multiplexing characteristics, please refer to section 5.5 of this document.
peripheral interfaces revised november 2010 cm - a510 reference guide 24 4.8 uart?s the cm - a510 incorporates three general purpose uart?s. the following features are supported: 16550 compatibility 16 - byte fifo for receiver and 16 - byte fifo for transmitter programmable ba ud rate of up to 900 kbps configurable data format table 18 uart signals signal name pin # type description availability configuration?group 1 - uart uart1_txd p1 - 114 o uart serial data out uart1_rxd p1 - 112 i uart serial data in always available. uart1 uart - 2 uart2_txd p1 - 64 o uart serial data out uart2_rxd p1 - 66 i uart serial data in always available. each pin is configured separately. uart - 3 uart3_txd p1 - 72 o uart serial data out uart3_rxd p1 - 61 i uart serial data in uart3_cts p1 - 70 o uart clear to send uart3_rts p1 - 68 i uart request to send always available. each pin is configu red separately. note: uart signals are multiplexed with signals used for other interfaces. for multiplexing characteristics, please refer to section 5.5 of this document. note: uart - 1 signals can only be configured on a group basis. only the entire group may be assigned with a specific function. individual uart - 1 signals cannot be configur ed separately for different functions. 4.9 rs232 the cm - a510 incorporates a single rs232 port. the following features are supported: 16550 compatibility 16 - byte fifo for receiver and 16 - byte fifo for transmitter programmable baud rate of up to 250 kbps configu rable data format rs - 232 bus - pin esd protection exceeds 15 kv using the human - body model the rs232 port is derived from uart - 0 of the armada 510 soc. note: the rs232 port operates at rs232 voltage levels.
peripheral interfaces revised november 2010 cm - a510 reference guide 25 table 19 rs232 signal s signal name pin # type description availability rs232_txd p1 - 119 o rs232 serial data out rs232_rxd p1 - 117 i rs232 serial data in rs232_cts p1 - 123 i rs232 clear to send rs232_rts p1 - 121 o rs232 request to send always available. 4.10 mmc / sd / sdio the cm - a510 features two multimedia card high - speed/secure data/secure digital i/o (mmc / sd / sdio) host interfaces. the following main features are supported: 1 - bit/4 - bit sd memory, sdio and mmc cards up to 50mhz (sd phy rev 1.1 high speed) sdhc (sd phy rev 2.0) dma and pio operation for additional details, please refer to section 23 of ?88ap510 functional specifications?. note: mmc/sd/sdio signals are multiplexed with signals used for other interfaces. for multiplexing characteristics, please refer to secti on 5.5 of this document. note: mmc/sd/sdio signals can only be configured on a group basis. only the entire group may be assigned with a specific function. individual signals cannot be configured separately for different functions. table 20 mmc/sd/sdio signals signal name pin # type description availability configuration? group 0 - sd sd0_data0 p2 - 54 io data signal 0 sd0_data1 p2 - 56 io data signal 1 sd0_data 2 p2 - 58 io data signal 2 sd0_data3 p2 - 60 io data signal 3 sd0_cmd p2 - 78 io command signal sd0_clk p2 - 76 o clock output always available. sd - 0 sd0_cd p1 - 68 i card detection input sd0_wp p1 - 70 i card write protectio n input always available. each pin is configured separately. sd - 1 sd1_data0 p2 - 61 io data signal 0 sd1_data1 p2 - 63 io data signal 1 sd1_data2 p2 - 65 io data signal 2 sd1_data3 p2 - 69 io data signal 3 sd1_cmd p2 - 75 io command signal sd1_ clk p2 - 73 o clock output only available without the ?w? configuration option. sd - 1
peripheral interfaces revised november 2010 cm - a510 reference guide 26 4.11 touch - screen the cm - a510 features a resistive touch - screen interface. the interface supports 4 - wire touch panels. the touch - screen controller is connected to the spi - 1 interface of the armada 510 soc. table 21 touch - screen signals signal name pin # type description availability ts_x+ p1 - 23 ai touch screen x+ (right) ts_x - p1 - 21 ai touch screen x - (left) ts_y+ p1 - 29 ai touch screen y+ (top) ts_y - p1 - 27 ai touch screen y - (bottom) only available with the ?i? configuration option.
peripheral interfaces revised november 2010 cm - a510 reference guide 27 4.12 gpio the cm - a510 provides up to 44 gpio signals. these signals can be configured for the following applications: data input / output interrupt generation for additional details, please refer to section 28 of ?88ap510 fun ctional specifications?. note: gpio signals are multiplexed with signals used for other interfaces. for multiplexing characteristics, please refer to section 5.5 of this document. note: certain gpio signals can only be configured on a group basis. only the entire group may be assigned with a specific function. individual signals cannot be configured separately for different functions. table 22 gpio signals cm - a510 signal armada 510 signal availability configuration? group p1 - 64 gpio_14 available with all configurations. muxed with uart - 2, ssp. p1 - 66 gpio_15 available with all configurations. muxed with uart - 2. p1 - 68 gpio_16 available with all co nfigurations. muxed with uart - 3, sd - 0. p1 - 70 gpio_17 available with all configurations. muxed with uart - 3, sd - 0, i2c - 2. p1 - 72 gpio_18 available with all configurations. muxed with uart - 3, sd - 0. p1 - 61 gpio_19 available with all configurations. muxed w ith uart - 3, i2c - 2. p1 - 63 gpio_20 only available without ?i? option. muxed with spi - 1, sd - 0. p1 - 65 gpio_21 only available without ?i? option. muxed with spi - 1, sd - 0, ssp. p1 - 69 gpio_22 only available without ?i? option. muxed with spi - 1, ssp. p1 - 71 gpio_23 only available without ?i? option. muxed with spi - 1, ssp. each pin is configured separately. p1 - 40 gpio_24 available with all configurations. muxed with camera interface. p1 - 42 gpio_25 available with all configurations. muxed with camera interface. p1 - 44 gpio_26 availabl e with all configurations. muxed with camera interface. p1 - 46 gpio_27 available with all configurations. muxed with camera interface. p1 - 48 gpio_28 available with all configurations. muxed with camera interface. p1 - 45 gpio_29 available with all confi gurations. muxed with camera interface. p1 - 47 gpio_30 available with all configurations. muxed with camera interface. p1 - 49 gpio_31 available with all configurations. muxed with camera interface. p1 - 52 gpio_32 available with all configurations. muxe d with camera interface. p1 - 51 gpio_33 available with all configurations. muxed with camera interface. p1 - 53 gpio_34 available with all configurations. muxed with camera interface. p1 - 57 gpio_35 available with all configurations. muxed with camera in terface. p1 - 54 gpio_38 available with all configurations. muxed with camera interface. p1 - 56 gpio_39 available with all configurations. muxed with camera interface. camera p2 - 46 gpio_40 available with all configurations. muxed with sd - 0. p2 - 78 gpio_41 available with all configurations. muxed with sd - 0. p2 - 54 gpio_42 available with all configurations. muxed with sd - 0. p2 - 56 gpio_43 available with all configurations. muxed with sd - 0. p2 - 58 gpio_44 available with all configurations. muxed with sd - 0. p2 - 60 gpio_45 available with all configurations. muxed with sd - 0. sd - 0 p2 - 73 gpio_46 only available without ?w? option. muxed with sd - 1. p2 - 75 gpio_47 only available without ?w? option. muxed with sd - 1. p2 - 61 gpio_48 only available without ?w? opti on. muxed with sd - 1. p2 - 63 gpio_49 only available without ?w? option. muxed with sd - 1. p2 - 65 gpio_50 only available without ?w? option. muxed with sd - 1. p2 - 69 gpio_51 only available without ?w? option. muxed with sd - 1. sd - 1
peripheral interfaces revised november 2010 cm - a510 reference guide 28 cm - a510 signal armada 510 signal availability configuration? group p2 - 47 gpio_52 available with all configurations. muxed with i2s. p2 - 45 gpio_53 available with all configurations. muxed with i2s. p2 - 53 gpio_54 available with all configurations. muxed with i2s. p2 - 49 gpio_55 available with all configurations. muxed with i2s. p2 - 5 1 gpio_56 available with all configurations. muxed with i2s, i2c - 2. p2 - 41 gpio_57 available with all configurations. muxed with s/pdif, i2c - 2. digital audio p1 - 112 gpio_62 available with all configurations. muxed with uart - 1. p1 - 114 gpio_63 available with al l configurations. muxed with uart - 1. uart - 1 4.13 camera interface the cm - a510 camera interface is implemented with the camera sub - system of the armada 510 soc. the camera interface provides the system interface and the processing capability to connect raw image - sens or modules to the cm - a510. for additional details, please refer to section 17 of the ?88ap510 functional specifications?. note: camera signals can only be configured on a group basis. only the entire group may be assigned with a specific function. individu al signals cannot be configured separately for different functions. table 23 camera interface signals signal name pin # type description availability configuration? group cam_clk p1 - 57 i pixel clock ca m_hsync p1 - 51 i horizontal sync input cam_vsync p1 - 53 i vertical sync input cam_snr_ctl0 p1 - 54 o sensor control 0 cam_snr_ctl1 p1 - 56 o sensor control 1 cam_mclk p1 - 52 o pixel master clock cam_d0 p1 - 40 i pixel input data line 0 cam_d1 p1 - 4 2 i pixel input data line 1 cam_d2 p1 - 44 i pixel input data line 2 cam_d3 p1 - 46 i pixel input data line 3 cam_d4 p1 - 48 i pixel input data line 4 cam_d5 p1 - 45 i pixel input data line 5 cam_d6 p1 - 47 i pixel input data line 6 cam_d7 p1 - 49 i pixel input data line 7 always available. camera
peripheral interfaces revised november 2010 cm - a510 reference guide 29 4.14 i 2 c the cm - a510 features up to three general - purpose i 2 c interfaces. the following features are supported: master / slave operation standard mode (up to 100k bits/s) for additional details, please refer to section 25 of ?88ap510 functional specifications?. note: i2c signals are multiplexed with signals used for other interfaces. for multiplexing characteristics, please refer to section 5.5 of this document. note: certain i2c signals can only be config ured on a group basis. only the entire group may be assigned with a specific function. individual signals cannot be configured separately for different functions. table 24 i 2 c signals signal name pin # type description availabi lity configuration? group i2c - 0 i2c0_sda p2 - 25 iod i2c serial data line. open drain buffer. pulled up to 3.3v i2c0_scl p2 - 27 iod i2c serial clock line. open drain buffer. pulled up to 3.3v always available. not configurable. dedicated to i2c. i2c - 1 i 2c1_sda p1 - 70 iod i2c serial data line. open drain buffer. pulled up to 3.3v i2c1_scl p1 - 61 iod i2c serial clock line. open drain buffer. pulled up to 3.3v always available. each pin is configured separately. i2c - 2 i2c2_sda p2 - 51 iod i2c serial data l ine. open drain buffer. pulled up to 3.3v i2c2_scl p2 - 41 iod i2c serial clock line. open drain buffer. pulled up to 3.3v always available. digital audio
peripheral interfaces revised november 2010 cm - a510 reference guide 30 4.15 spi the cm - a510 features an spi interface implemented with the armada 510 spi controller. for addit ional details, please refer to section 24 of ?88ap510 functional specifications?. note: spi signals are multiplexed with signals used for other interfaces. for multiplexing characteristics, please refer to section 5.5 of this document. table 25 spi signals signal name pin # type description availability configuration? group spi1_clk p1 - 71 o spi clock spi1_cs p1 - 65 o spi chip select spi1_miso p1 - 63 i spi data input spi1_mosi p1 - 69 o spi data output only available without the ?i? configuration option. each pin is configured separatel y. 4.16 ssp the cm - a510 features an ssp interface implemented with the armada 510 ssp controller. the interface supports the following features: complia nt with texas instruments? synchronous serial protocol programmable data sample sizes of 8, 16, 18 and 32 - bits up to 24mhz serial clock rate master and slave operation modes for additional details, please refer to section 27 of ?88ap510 functional specific ations?. note: ssp signals are multiplexed with signals used for other interfaces. for multiplexing characteristics, please refer to section 5.5 of this document. table 26 ssp signal s signal name pin # type description availability configuration? group ssp_sfrm p1 - 65 io serial frame indicator ssp_rxd p1 - 64 i serial receive data ssp_txd p1 - 69 o serial transmit data ssp_sclk p1 - 71 io serial clock only available without the ?i? configuration option. each pin is configured separately.
peripheral interfaces revised november 2010 cm - a510 reference guide 31 4.17 jtag the cm - a510 jtag interface is derived from the armada 510 soc jtag port. the armada 510 target debug interface uses the five standard ieee 1149.1 (jtag) signals (ntrst, tck, tms, tdi and tdo). for additional details, please refer to section 8 of ?88ap510 hardware specifications?. table 27 jtag signals signal name pin # type description jtag_clk p2 - 90 i test clock jtag_tdo p2 - 94 o test data output jtag_tdi p2 - 92 i test data input jtag_tms p2 - 96 io test mode select jtag_ntrst p2 - 88 i test logic reset
system logic revised november 2010 cm - a510 reference guide 32 5 system logic 5.1 power management 5.1.1 power rails the cm - a510 is powered by a single 5v power rail. table 28 power signals signal name type descr iption vin_5v p main power supply. typical voltage ? 5v. vcc_rtc p rtc back - up battery power input. connect to a 3v coin - cell lithium battery. leave unconnected if rtc back - up is not required. gnd p common ground. 5.1.2 low power mode to be added in a future revision of this document. 5.2 reset the nrst_in signal is the main system reset that invokes a global reset that affects every module on the cm - a510. the sysrst_nout is a dedicated system reset out signal that can be used to reset baseboard peripheral device s. sysrst_nout is asserted low for 20ms on power - on - reset and nrst_in de - assertion. table 29 reset signals signal name pin # type description nrst_in p2 - 33 ipu main system reset input. pulled up to 3.3v sysrst_nout p2 - 20 o sy stem reset output. leave disconnected if not used. 5.3 boot options the cm - a510 supports the following boot options: boot from onboard spi nor flash boot from external hard drive connected to the sata interface the boot device is selected with the boot_source signal. the standard boot option is designed for normal system operation with the on - board spi nor flash acting as the boot media. the alternate boot option is intended mainly for system debug and production. it can also be used for normal operation with an external sata hard drive acting as the boot media. table 30 boot options boot option boot_source signal input boot device standard unconnected. on - board flash alternate pulled to 3.3v with 1k resistance. external sata hard drive
system logic revised november 2010 cm - a510 reference guide 33 table 31 boot selection signals signal name pin # type description boot_source p2 - 117 i boot selection. pulled down with 8.2k. leave disconnected for standard boot sequence. 5.4 system and miscellaneous signals table 32 system signals signal name pin # type description flash_nwp p2 - 46 i spi nor flash write protection. active low. reserved p2 - 35 i reserved for future use. leave unconnected. reserved p2 - 37 o reserved for future use. leave unco nnected. reserved p2 - 39 i reserved for future use. leave unconnected. reserved p2 - 119 i reserved for future use. leave unconnected. reserved p2 - 121 i reserved for future use. leave unconnected. reserved p2 - 28 - reserved for debug and production. leave unconnected. reserved p2 - 30 - reserved for debug and production. leave unconnected. reserved p2 - 32 - reserved for debug and production. leave unconnected. reserved p2 - 34 - reserved for debug and production. leave unconnected. 5.5 signal multiplexing chara cteristics armada 510 pins have up to six alternate function modes. the table below provides a description of signal multiplexing. function names marked with gray shading denote the default function intended in the cm - a510 design. note: certain software - co nfigurable multi - purpose signals can only be configured on a group basis. only the entire group may be assigned with a specific function. signals within a group cannot be configured separately for different functions. table 33 signal multiplexing pin # mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 config. group p1 - 40 gpio24 cam_d0 - - - - - p1 - 42 gpio25 cam_d1 - - - - - p1 - 44 gpio26 cam_d2 - - - - - p1 - 45 gpio29 cam_d5 - - - - - p1 - 46 gpio27 cam_d3 - - - - - p1 - 47 gpio30 cam_d6 - - - - - p1 - 48 gpio28 cam_d4 - - - - - p1 - 49 gpio31 cam_d7 - - - - - p1 - 51 gpio33 cam_hsync - - - - - p1 - 52 gpio32 cam_mclk - - - - - p1 - 53 gpio34 cam_vsync - - - - - p1 - 54 gpio38 cam_snr_ctl0 - - - - - p1 - 56 gpio39 cam_s nr_ctl1 - - - - - p1 - 57 gpio35 cam_clk - - - - - camera p1 - 61 gpio19 - uart3_rxd - i2c1_sck - - none p1 - 63 gpio20 - - sd1_cd - sd0_cd spi1_miso none p1 - 64 gpio14 - uart2_txd - sd1_pwren ssp_rxd - none p1 - 65 gpio21 uart1_rts - sd1_wp ssp_sfrm sd0_wp spi1_cs none p1 - 66 gpio15 - uart2_rxd - - - - none p1 - 68 gpio16 - uart3_rts sd0_cd - - - none p1 - 69 gpio22 uart1_cts - sd1_pwren ssp_txd sd0_pwren spi1_mosi none p1 - 70 gpio17 - uart3_cts sd0_wp i2c1_sda - - none p1 - 71 gpio23 - - - ssp_sclk - spi1_clk none
system logic revised november 2010 cm - a510 reference guide 34 pin # mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 config. group p 1 - 72 gpio18 - uart3_txd sd0_pwren - - - none p1 - 112 gpio62 uart1_rxd - - - - - p1 - 114 gpio63 uart1_txd - - - - - uart - 1 p2 - 41 gpio57 spdifo i2c2_sck - - - - p2 - 45 gpio53 i2s1_bclk - - - - - p2 - 47 gpio52 i2s1_di - - - - - p2 - 49 gpio55 i2s1_do - - - - - p2 - 51 gpio56 i2s1_lrclk i2c2_sda - - - - p2 - 53 gpio54 i2s1_mclk - - - - - digital audio p2 - 54 gpio42 sd0_data0 - - - - - p2 - 56 gpio43 sd0_data1 - - - - - p2 - 58 gpio44 sd0_data2 - - - - - p2 - 60 gpio45 sd0_data3 - - - - - sdio - 0 p2 - 61 gpio4 8 sd1_data0 - - - - - p2 - 63 gpio49 sd1_data1 - - - - - p2 - 65 gpio50 sd1_data2 - - - - - p2 - 69 gpio51 sd1_data3 - - - - - p2 - 73 gpio46 sd1_clk - - - - - p2 - 75 gpio47 sd1_cmd - - - - - sdio - 1 p2 - 76 gpio40 sd0_clk - - - - - p2 - 78 gpio41 sd0 _cmd - - - - - sdio - 0 5.6 rtc the cm - a510 rtc is implemented with the internal rtc of the armada 510 soc. the rtc provides time and calendar information, timed interrupt generation and alarm wake - up event functionality. additionally, a backup battery can keep the r tc running to maintain clock and time information even if the main supply is not present. the backup battery should be connected to the vcc_rtc power input. for additional details, please refer to section 29 of ?88ap510 functional specifications?. 5.7 led the cm - a510 features a single general purpose green led controlled by gpio65 of the armada 510 soc. the led is on when gpio65 is set high.
baseboard interfa ce revised november 2010 cm - a510 reference guide 35 6 baseboard interface the cm - a510 connects to the baseboard through p1 and p2 - 0.6 mm pitch 140 - pin connectors. 6.1 connector pin - out table 34 connector p1 pin # cm - a510 signal name reference section pin # cm - a510 signal name reference section p1 - 1 lan0_mdip1 4.2.1 p1 - 2 lan0_mdip0 4.2.1 p1 - 3 lan0_mdin1 4.2.1 p1 - 4 lan0_mdin0 4.2.1 p1 - 5 lan0_led1 4.2.1 p1 - 6 lan0_led0 4.2.1 p1 - 7 vin_5v 5.1.1 p1 - 8 gnd 5.1.1 p1 - 9 lan0_mdip3 4.2.1 p1 - 10 lan0_mdip 2 4.2.1 p1 - 11 lan0_mdin3 4.2.1 p1 - 12 lan0_mdin2 4.2.1 p1 - 13 lan0_led2 4.2.1 p1 - 14 gnd 5.1.1 p1 - 15 n.c. p1 - 16 n.c. p1 - 17 n.c. p1 - 18 n.c. p1 - 19 vin_5v 5.1.1 p1 - 20 n.c. p1 - 21 ts_x - 4.11 p1 - 22 n.c. p1 - 23 ts_x+ 4.11 p1 - 24 n.c. p1 - 25 n.c. p1 - 26 gnd 5.1.1 p1 - 27 ts_y - 4.11 p1 - 28 vga_r 4.1 p1 - 29 ts_y+ 4.11 p1 - 30 vga_g 4.1 p1 - 31 vin_5v 5.1.1 p1 - 32 vga_b 4.1 p1 - 33 n.c. p1 - 34 vga_hsync 4.1 p1 - 35 n.c. p1 - 3 6 vga_vsync 4.1 p1 - 37 vcc_rtc 5.1.1 p1 - 38 gnd 5.1.1 p1 - 39 n.c. p1 - 40 cam_d0 gpio24 4.13 4.12 p1 - 41 n.c. p1 - 42 cam_d1 gpio25 4.13 4.12 p1 - 43 vin_5v 5.1.1 p1 - 44 cam_d2 gpio26 4.13 4.12 p1 - 45 cam_d5 gpio29 4.13 4.12 p1 - 46 cam_d3 gpio27 4.13 4.12 p1 - 47 cam_d6 gpio30 4.13 4.12 p1 - 48 cam_d4 gpio28 4.13 4.12 p1 - 49 cam_d7 gpio31 4.13 4.12 p1 - 50 gnd 5.1.1 p1 - 51 cam_hsync gpio33 4.13 4.12 p1 - 52 cam_mclk gpio32 4.13 4.12 p1 - 53 cam_vsync gpio34 4.13 4.12 p1 - 54 cam_snr_ctl0 gpio38 4.13 4.12 p1 - 55 vin_5v 5.1.1 p1 - 56 cam_snr_ctl1 gpio39 4.13 4.12 p1 - 57 cam_clk gpio35 4.13 4.12 p1 - 58 cam_tw_sck 4.13 p1 - 59 n.c. p1 - 60 cam_tw_sda 4.13 p1 - 61 uart3_rxd i2c1_scl gpio19 4.8 4.14 4.12 p1 - 62 gnd 5.1.1 p1 - 63 spi1_miso sd0_cd gpio20 4.15 4.10 4.12 p1 - 64 uart2_txd ssp_rxd gpio14 4.8 4.16 4.12 p1 - 65 spi1_cs sd0_wp ssp_sfrm gpio21 4.15 4.10 4.16 4.12 p1 - 66 uart2_rxd gpio15 4.8 4.12 p1 - 67 vin _5v 5.1.1 p1 - 68 uart3_rts sd0_cd gpio16 4.8 4.10 4.12
baseboard interface revised november 2010 cm - a510 reference guide 36 pin # cm - a510 signal name reference section pin # cm - a510 signal name reference section p1 - 69 spi1_mosi sd0_pwren ssp_txd gpio22 4.15 4.10 4.16 4.12 p1 - 70 uart3_cts sd0_wp i2c1_sda gpio17 4.8 4.10 4.14 4.12 p1 - 71 spi1_clk ssp_sclk gpio23 4.15 4.16 4.12 p1 - 72 uart3_txd sd0_pwren gpio18 4.8 4.10 4.12 p1 - 73 n.c. p1 - 74 gnd 5.1.1 p1 - 75 lcd_d0 4.1 p1 - 76 lcd_d1 4.1 p1 - 77 lcd_d2 4.1 p1 - 78 lcd_d3 4.1 p1 - 79 vin_5v 5.1.1 p1 - 80 n.c. p1 - 81 lcd_d4 4.1 p1 - 82 lcd_d5 4.1 p1 - 83 lcd_d6 4.1 p1 - 84 lcd_d7 4.1 p1 - 85 lcd_d8 4.1 p1 - 86 gnd 5.1.1 p1 - 87 lcd_d9 4.1 p1 - 88 lcd_d10 4.1 p1 - 89 lcd_d11 4.1 p1 - 90 lcd_d12 4.1 p1 - 91 vin_5v 5.1.1 p1 - 92 lcd_d13 4.1 p1 - 93 lcd_d14 4.1 p1 - 94 lcd_d15 4. 1 p1 - 95 lcd_d16 4.1 p1 - 96 lcd_d17 4.1 p1 - 97 lcd_d18 4.1 p1 - 98 gnd 5.1.1 p1 - 99 lcd_d19 4.1 p1 - 100 lcd_d20 4.1 p1 - 101 lcd_d21 4.1 p1 - 102 lcd_d22 4.1 p1 - 103 vin_5v 5.1.1 p1 - 104 lcd_d23 4.1 p1 - 105 lcd_e 4.1 p1 - 106 n.c. p1 - 107 lcd_vsync 4.1 p1 - 108 lcd_clk 4.1 p1 - 109 lcd_hsync 4.1 p1 - 110 gnd 5.1.1 p1 - 111 n.c. p1 - 112 uart1_rxd gpio62 4.8 4.12 p1 - 113 n.c. p1 - 114 uart1_txd gpio63 4.8 4.12 p1 - 115 vin_5v 5.1.1 p1 - 116 n.c. p1 - 117 rs232_rxd 4.9 p1 - 118 n.c. p1 - 119 rs232_txd 4.9 p1 - 120 n.c. p1 - 121 rs232_rts 4.9 p1 - 122 gnd 5.1.1 p1 - 123 rs232_cts 4.9 p1 - 124 n.c p1 - 125 n.c. p1 - 126 usb2_cpen 4.5 p1 - 127 vin_5v 5.1.1 p1 - 128 usb1_cpen 4.5 p1 - 129 usb2_dn 4.5 p1 - 130 usb0_dn 4.5 p1 - 131 usb2_dp 4.5 p1 - 132 usb0_dp 4.5 p1 - 133 usb3_cpen 4.5 p1 - 134 gnd 5.1.1 p1 - 135 usb3_dn 4.5 p1 - 136 usb1_dn 4.5 p1 - 137 usb3_dp 4.5 p1 - 138 usb1_dp 4.5 p1 - 139 vin_5v 5.1.1 p1 - 140 n.c table 35 connector p2 pin # cm - a510 signal name reference section pin # cm - a510 signal name reference section p2 - 1 lan1_mdip1 4.2.2 p2 - 2 lan1_mdip0 4.2.2 p2 - 3 lan1_mdin1 4.2.2 p2 - 4 lan1_mdin0 4.2.2 p2 - 5 lan1_led1 4.2.2 p2 - 6 lan1_led0 4.2.2 p2 - 7 gnd 5.1.1 p2 - 8 gnd 5.1.1 p2 - 9 lan1_mdip3 4.2.2 p2 - 10 lan1_mdi p2 4.2.2 p2 - 11 lan1_mdin3 4.2.2 p2 - 12 lan1_mdin2 4.2.2 p2 - 13 lan1_led2 4.2.2 p2 - 14 gnd 5.1.1 p2 - 15 pcie1_c lkreq 4.3 p2 - 16 n.c. p2 - 17 pcie0_clkreq 4.3 p2 - 18 n.c. p2 - 19 vin_5v 5.1.1 p2 - 20 sysrst_outn p2 - 21 n.c. p2 - 22 n.c. p2 - 23 n.c. p2 - 24 n.c. p2 - 25 i2c0_sda 4.14 p2 - 26 gnd 5.1.1 p2 - 27 i2c0_scl 4.14 p2 - 28 reserved 5.4 p2 - 29 n.c. p2 - 30 reserved 5.4 p2 - 31 vin_5v 5.1.1 p2 - 32 reserved 5.4 p2 - 33 nrst_in 5.2 p2 - 34 reserved 5.4 p2 - 35 reserved 5. 4 p2 - 36 n.c.
baseboard interface revised november 2010 cm - a510 reference guide 37 pin # cm - a510 signal name reference section pin # cm - a510 signal name reference section p2 - 37 reserved 5.4 p2 - 38 gnd 5.1.1 p2 - 39 reserved 5.4 p2 - 40 n.c. p2 - 41 spdif i2c2_scl gpio57 4.7.3 4.14 4.12 p2 - 42 n.c. p2 - 43 vin_5v 5.1.1 p2 - 44 n.c. p2 - 45 i2s1_bclk gpio53 4.7.2 4.12 p2 - 46 flash_nwp 5.4 p2 - 47 i2s1_sdi gpio52 4.7.2 4.12 p2 - 48 n.c. p2 - 49 i2s1_sdo gpio55 4.7.2 4.12 p2 - 50 n.c. p2 - 51 i2s1_lrclk i2c2_sda gpio56 4.7.2 4.14 4.12 p2 - 52 gnd 5.1.1 p2 - 53 i2s1_mclk gpio54 4.7.2 4.12 p2 - 54 sd0_data0 gpio42 4.10 4.12 p2 - 55 vin_5v 5.1.1 p2 - 56 sd0_data1 gpio43 4.10 4.12 p2 - 57 n.c. p2 - 58 sd0_data2 gpio44 4.10 4.12 p2 - 59 n.c. p2 - 60 sd0_data3 gpio45 4.10 4.12 p2 - 61 sd1_data0 gpio48 4.10 4.12 p2 - 62 gnd 5.1.1 p2 - 63 sd1_data1 gpio49 4.10 4.12 p2 - 64 n.c. p2 - 65 sd1_data2 gpio50 4.10 4.12 p2 - 66 n.c. p2 - 67 vin_5v 5.1.1 p2 - 68 n.c. p2 - 69 sd1_data3 gpio51 4.10 4.12 p2 - 70 n.c. p2 - 71 n.c. p2 - 72 n.c. p2 - 73 sd1_clk gpio46 4.10 4.12 p2 - 74 gnd 5.1.1 p2 - 75 sd1_cmd gpio47 4.10 4.12 p2 - 76 sd0_clk gpio40 4.10 4.12 p2 - 77 n.c. p2 - 78 sd0_cmd gpio41 4.10 4.12 p2 - 79 vin_5v 5.1.1 p2 - 80 n.c. p2 - 81 pcie1_clk_n 4.3 p2 - 82 n.c. p2 - 83 pcie1_clk_p 4.3 p2 - 84 n.c. p2 - 85 n.c. p2 - 86 gnd 5.1.1 p2 - 87 n.c. p2 - 88 jtag_ntrst 0 p2 - 89 sysrst_inn 5.2 p2 - 90 jtag_clk 0 p2 - 91 vin_5v 5.1.1 p2 - 92 jtag_tdi 0 p2 - 93 n.c. p2 - 94 jtag_tdo 0 p2 - 95 n.c. p2 - 96 jtag_tms 0 p2 - 97 n.c. p2 - 98 gnd 5.1.1 p2 - 99 pcie0_clk_n 4.3 p2 - 100 n.c. p2 - 101 pcie0_clk_p 4.3 p2 - 102 n.c. p2 - 103 vin_5v 5.1.1 p2 - 104 n.c. p2 - 105 pcie1_rx_n 4.3 p2 - 106 pcie0_rx_n 4.3 p2 - 107 pcie1_rx_p 4. 3 p2 - 108 pcie0_rx_p 4.3 p2 - 109 n.c. p2 - 110 gnd 5.1.1 p2 - 111 pcie1_tx_n 4.3 p2 - 112 pcie0_t x_n 4.3 p2 - 113 pcie1_tx_p 4.3 p2 - 114 pcie0_tx_p 4.3 p2 - 115 vin_5v 5.1.1 p2 - 116 n.c. p2 - 117 boot_scr0 5.3 p2 - 118 sata_rx - 4.4 p2 - 119 reserved 5.4 p2 - 120 sata_rx+ 4.4 p2 - 121 reserved 5.4 p2 - 122 gnd 5.1.1 p2 - 123 a udio_gnd 4.7.1 p2 - 124 sata_tx - 4.4 p2 - 125 mic_bias 4.7.1 p2 - 126 sata_tx+ 4.4 p2 - 127 vin_5v 5.1.1 p2 - 128 n. c. p2 - 129 mic_in 4.7.1 p2 - 130 n.c. p2 - 131 audio_in_r 4.7.1 p2 - 132 n.c. p2 - 133 audio_in_l 4.7.1 p2 - 134 gnd 5.1.1
baseboard interface revised november 2010 cm - a510 reference guide 38 pin # cm - a510 signal name reference section pin # cm - a510 signal name reference section p2 - 135 vin_5v 5.1.1 p2 - 136 usb3_novc 4.5 p2 - 137 audio_out_l 4.7.1 p2 - 138 usb2_novc 4.5 p2 - 139 audio_out_r 4.7.1 p2 - 140 usb1_ novc 4.5 6.2 connector type table 36 connector type part reference mfg. cm - a510 connector p/n baseboard (mating) connector p/n p1, p2 amp 1 - 5353183 - 0 1 - 5353190 - 0 or con140 mating connectors and stand offs are available from compulab, see [prices] >> [accessories] links at compulab's website. compulab's p/n for the amp 1 - 5353190 - 0 connector is "con140". 6.3 mechanical drawings figure 3 cm - a510 top
baseboard interface revised november 2010 cm - a510 reference guide 39 figure 4 cm - a510 bottom (x - ray view - as seen from top side) 1. all dimensions are in millimeters. 2. height of all components is <3mm. 3. baseboard connectors provide 4mm board - to - board clearance. 4. board thickness is 1.6mm. mechanical drawings are available in dxf format from compulab's website, following [developer] >> [cm - a510] >> [cm - a510 - dimensions and connectors location] links.
baseboard interface revised november 2010 cm - a510 reference guide 40 6.4 standoffs the cm - a510 has four mounting holes for standoffs. standoffs are implemented with three parts: screw, spacer and nut. table 37 standoffs part description manufacturer and p/n screw m2, 10 mm length fci 95121 - 005 acton inoxpro bf22102010 world bridge machinery 380j52080 spacer m2 x 4 thread, 4.2 mm length hirosugi asu - 2004 mac8 2sp - 4 world br idge machinery m2, l=4.2 mm nut m2, 1.6 - 2.0mm width fci 92869 - 001 (or 002) acton inoxpro bg12102000 bossard 1241397 (din934 - a2 m2) world bridge machinery 381a52000
operational characteristics revised november 2010 cm - a510 reference guide 41 7 operational characte ristics 7.1 absolute maximum ratings table 38 absolute maximum ratings parameter min typ max unit main power supply voltage (vin_5v) - 0.3 6.0 v vcc_rtc - 0.3 4.0 v 7.2 recommended operating conditions table 39 recommended operating conditions parameter min typ max unit m ain power supply voltage (vin_5v) 4.75 5.0 5.25 v rtc backup battery voltage (vcc_rtc) 2.2 3.3 3.45 v 7.3 dc electrical characteristics table 40 dc electrical characteristics parameter operating conditions min typ max unit 3.3v digital i/o v ih 2 3.6 v v il - 0.3 0.8 v v oh 2.4 v v ol 0.4 v i 2 c (open drain with internal pull up to 3.3v) v ih 2.3 3.8 v v il - 0.5 1.0 v v ol iol = 3 ma - 0.4 v irs232 tx voltage swing 5 5.4 v rx voltage swing 25 v 7.4 power con sumption to be added in a future revision of this document. 7.5 esd performance table 41 esd performance interface esd performance usb host 8 kv esd using hbm rs232 15 kv esd using hbm
operational characteristics revised november 2010 cm - a510 reference guide 42 7.6 thermal characteristics power dissipation characteristics vary depending on armada soc operating frequency and average workload. table 42 thermal characteristics soc operating frequency operational workload thermal conditions t between soc case and ambient temperature full 60c 1ghz idle 45c full 45c 800mhz idle operating in open - air, no heat - plate. ambient temperature - 25c. 35c when ambient temperature exceeds 3 5c or when t > 4 5 c, the cm - a510 should be provi ded with a heat dissipation solution. the following solutions may be used: heat - plate supplied by compulab. for further details, please refer to section 8.4 of this document. heat extruder integrated into custom er designed enclosure enforced airflow 7.7 operating temperature ranges the cm - a510 is available with three options of operating temperature range. table 43 cm - a510 temperature range options range temp. description commercial 0 o to 70 o c sample boards from each batch are tested for the lower and upper temperature limits. individual boards are not tested. extended - 20 o to 70 o c every board undergoes a short test for the lower limit ( - 20 o c) qualification. industrial - 40 o to 85 o c every board is extensively tested for both lower and upper limits and at several midpoints.
application notes revised november 2010 cm - a510 reference guide 43 8 application notes 8.1 baseboard design guidelines ensure that all vin_5v and gnd power pins are connected. major power rails - vin_5v and gnd must be implemented by planes, rather than traces. using at least two planes is essential to ensure the system's signal quality, because the planes provide a current return path for all interface signals. it is recommended to put several 100nf and 10/100uf capacitors between vin_5v and gnd near the mating connectors. it is recommended to connect the standoff holes of the baseboard to gnd, in order to improve emc. except for a power connection, no other connection is mandatory for cm - a510 operation. all power - up circuitry and all required pull - ups/pull - downs are present on the module. if for some reason you decide to place an external pull - up or pull - down resistor on a certain signal (for example - on the gpio's), first check the documentation of that signal provided in this m anual. certain signals have on - board pull - up/pull - down resistors required for proper initialization. overriding their values by external components will disable board operation. you must be familiar with signal interconnection design rules. there are many sensitive groups of signals. for example: pci express, sata, ethernet and usb signals must be routed in differential pairs and by a controlled impedance trace. audio input must be decoupled from possible sources of baseboard noise. be careful when placing components under the cm - a510 module. the baseboard interface connector provides 4mm mating height. bear in mind that there are components on the underside of the cm - a510. maximum allowable height for components placed under the cm - a510 is 1mm. refer to the sb - a510 baseboard reference design schematics. 8.2 baseboard troubleshooting using grease solvent and a soft brush, clean the contacts of the mating connectors of both the module and the baseboard. remnants of soldering paste can prevent proper contact. take care to let the connectors and the module dry entirely before re - applying power ? otherwise corrosion may occur. using an oscilloscope, check the voltage levels and quality of the vin_5v power supply. it should be as specified in section 7.2 . check that there is no excessive ripple or glitches. first perform the measurements without plugging in the module. then plug in the module and measure again. measurement should be performed on the pins of the mating connector. using an oscilloscope, verify that the gnd pins of the mating connector are indeed at zero voltage level and that there is no ground bouncing. the module must be plugged in during the test. create a "minimum system" - only power, mating connectors, the module and a serial interface. check if the system starts properly. in system larger than the minimum, possible sources of disturbance could be: devices improperly driving the local bus
application notes revised november 2010 cm - a510 reference guide 44 external pull - up/pull - down resistors overriding the module?s on - board values, or any other component creating the same "overriding" effect faulty power supply in order to avoid possible sources of disturbance, it is strongly recommended to start with a minimal system and then to add/activate off - board devices one by one. check fo r the existence of soldering shorts between pins of mating connectors. even if the signals are not used on the baseboard, shorting them on the connectors can disable the module. an initial check can be performed using a microscope. however, if microscope i nspection finds nothing, it is advisable to check using an x - ray, because often, solder bridges are deep beneath the connector's body. note that solder shorts are the most frequent factor disabling module operation. check possible signal shorts due to err ors of baseboard pcb design or assembly. improper functioning of a custom baseboard can accidentally delete the cm - a510 boot - up code or even damage the module hardware permanently. before each activation attempt, check that your module is still functional with a compulab sb - a510 baseboard. it is recommended to assemble more than one baseboard for prototyping, in order to ease resolution of problems related to specific board assembly. 8.3 ethernet magnetics? implementation 8.3.1 magnetics? selection refer to the tab le below for compatible magnetic modules. designers should test and qualify magnetic modules before using them in an application. table 44 compatible magnetics vendor p/n package ude rb1 - 125bak1a integrated rj45 speed tech p6 5 - 101 - [1|2]ak9 integrated rj45 pulse engineering h5007 16 - pin soic pulse engineering h1251 16 - pin soic 8.3.2 magnetics? connection for magnetic modules connection, please refer to the sb - a510 reference design schematics. 8.4 heat - plate integration to be added in a future revision of this document.

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